1. Field of the Invention
The present invention relates to a reconfigurable circuit.
2. Description of the Related Art
FIG. 8 shows a diagram illustrating a configuration example of a reconfigurable circuit in which a configuration 0 is set, and FIG. 9 shows a diagram illustrating a configuration example of a reconfigurable circuit in which a configuration 1 is set. The reconfigurable circuit includes a network module 801. The network module 801 receives the input data of external input data terminals DI and outputs data from external output data terminals DO. Also, the network module 801 includes a first ALU (arithmetic and logic unit) 811, a second ALU 812, a third ALU 813, a fourth ALU 814, a counter 815 and a RAM 816. Each ALU 811-814 receives the input data of input terminals (a) and (b), and outputs an arithmetic result from an output terminal (o). The counter 815 receives the input data of input terminals (a) and (b), and outputs a counter value from an output terminal (o). The RAM 816 receives the input signals of a write terminal ‘write’ and a read terminal ‘read’, and outputs data from an output terminal (o).
First, the configuration 0 shown in FIG. 8 is described. The external input data terminals DI are connected to the input terminals (a) and (b) of the first ALU 811. For example, the first ALU 811 adds data of the input terminals (a) and (b). The output terminal (o) of the first ALU 811 is connected to the input terminal (a) of the third ALU 813. For example, the third ALU 813 performs a 4-bit shift operation of the data of the input terminal (a). The output terminal (o) of the third ALU 813 is connected to a ‘write’ terminal of the RAM 816. The RAM 816 performs, for example, a write operation.
Next, the configuration 1 shown in FIG. 9 is described. The external input data terminals DI are connected to the input terminal (a) of the fourth ALU 814 and the input terminal (a) of the counter 815. The output terminal (o) of the counter 815 is connected to the read terminal ‘read’ of the RAM 816. The RAM 816 performs, for example, a read operation. The output terminal (o) of the RAM 816 is connected to the input terminal (b) of the fourth ALU 814. For example, the fourth ALU 814 multiplies data of the input terminals (a) and (b). The output terminal (o) of the fourth ALU 814 is connected to external output data terminals DO.
FIG. 10 shows a diagram illustrating a configuration example of the network module 801. The network module 801 includes four (4) first switches 1001 and four (4) second switches 1002, and controls the switches 1001, 1002 based on a 64-bit control signal SEL. Each of switches 1001 and 1002 includes four input terminals and four output terminals, and can select one of the data input of the four input terminals and output the selected data from each output terminal. The 64-bit control signal SEL includes eight (8) 8-bit control signals. The eight switches 1001 and 1002 respectively perform control based on the eight 8-bit control signals. The input terminals of the first switch 1001 are connected to the above-mentioned arithmetic units 811-816 and the external input data terminals DI. The output terminals of the first switch 1001 are connected to the input terminals of the second switch 1002. The output terminals of the second switch 1002 are connected to the input terminals of the arithmetic units 811-816 and the external output data terminals DO.
As described above, the network module 801 can switch the functions of the arithmetic units 811-816 by switching the connections among the arithmetic units 811-816 according to the control signals SEL for configuration setting.
In Patent document 1 shown below, there is described a semiconductor integrated circuit including an input switch connected to a plurality of data input nodes, an output switch connected to a plurality of data output nodes, a first data path having an arithmetic unit and a first data holding circuit disposed between the above input switch and the above output switch, and a second data path having a second data holding circuit disposed between the input switch and the output switch, in which the first data holding circuit stores arithmetic result data of the arithmetic unit and the second data holding circuit holds data being input to any of the plurality of data input nodes.
In Patent document 2 shown below, there is described a semiconductor integrated circuit device having an embedded nonvolatile memory devices, a plurality of processors enabling functional modification by rewriting the memory devices and a unit for interconnecting the above plurality of processors in a programmable manner, formed on a single semiconductor substrate.    [Patent document 1] Japanese Patent Application Laid-open No. 2005-44329.    [Patent document 2] Japanese Patent Application Laid-open No. Hei 6-274459.
It is desirable that the network module 801 can connect from the output terminals of each arithmetic unit 811-816 to the input terminals of each arithmetic unit 811-816 arbitrarily for any combinations. However, as shown in FIG. 10, it is configured such that the wirings are used in common so as to reduce both the number of bits of the control signal SEL and the circuit scale. As a result, in some cases, there exist combinations of not being connectable, because of the occurrence of conflict in the network module 801.